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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a low cost parallel-port 16-bit soundport stereo codec AD1846 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features low cost, pin- and register-compatible alternative to ad1848 single-chip integrated ?d digital audio stereo codec supports the microsoft windows sound system* multiple channels of stereo input and output analog and digital signal mixing programmable gain and attenuation on-chip signal filters digital interpolation and decimation analog output low-pass sample rates from 5.5 khz to 48 khz 68-lead plcc package operation from +5 v supply byte-wide parallel interface to isa and eisa buses supports one or two dma channels and programmed i/o it provides a direct, byte-wide interface to both isa (at) and eisa computer buses for simplified implementation on a com- puter motherboard or add-in card. the AD1846 generates en- able and direction controls for ic buffers such as the 74_245. the AD1846 soundport stereo codec supports a dma re- quest/grant architecture for transferring data with the host com- puter bus. one or two dma channels can be supported. programmed i/o (pio) mode is also supported for control reg- ister accesses and for applications lacking dma control. two input control lines support mixed direct and indirect addressing of twenty-one internal control registers over this asynchronous interface. external circuit requirements are limited to a minimal number of low cost support components. anti-imaging dac output filters are incorporated on-chip. dac dynamic range exceeds 80 db over the 20 khz audio band. sample rates from 5.5 khz to 48 khz are supported from external crystals. the codec includes a stereo pair of ?d analog-to-digital con- verters and a stereo pair of ?d digital-to-analog converters. in- puts to the adc can be selected from four stereo pairs of analog signals: line, microphone (mic), auxiliary (aux) line #1, and post-mixed dac output. a software-controlled programmable gain stage allows independent gain for each channel going into the adc. the adcs output can be digitally mixed with the dacs input. (continued on page 9) playback req mux ?d a/d converter p a r a l l e l p o r t analog crystals analog supply digital supply l r gain l r m / a l a w ? ? oscillators reference l_mic r_mic r_line l_line r_aux1 l_aux1 ? r_out gain/atten/ mute l_aux2 r_aux2 ? digital m / a l a w data7:0 adr1:0 bus driver control capture req host dma interrupt external control control regs digital mix 16 ?d a/d converter 16 ?d d/a converter ?d d/a converter analog filter gain analog filter interpol interpol attenuate attenuate l_out atten/ mute atten/ mute gain/atten/ mute AD1846 power down v ref playback ack capture ack cs wr rd product overview the parallel-port AD1846 soundport ? stereo codec integrates key audio data conversion and control functions into a single in- tegrated circuit. the AD1846 is intended to provide a complete, single-chip audio solution for business audio and multimedia applications requiring operation from a single +5 v supply. *windows sound system is a trademark of microsoft corp. soundport is a registered trademark of analog devices, inc. functional block diagram
rev. a C2C AD1846Cspecifications standard test conditions unless otherwise noted dac output conditions post-autocalibrated temperature 25 c 0 db attenuation digital supply (v dd ) 5.0 v full scale (0 db) analog supply (v cc ) 5.0 v 16-bit linear mode word rate (f s ) 48 khz no output load input signal 1007 hz mute off analog output passband 20 hz to 20 khz adc input conditions fft size 4096 post-autocalibrated v ih 2.4 v 0 db gain v il 0.8 v C1.0 db relative to full scale v oh 2.4 v line input v ol 0.4 v 16-bit linear mode inputs driven with low impedance ( ? 50 w ) source analog input min typ max units full scale input voltage (rms values assume sine wave input) line 1 v rms 2.5 2.8 3.1 v p-p mic 1 v rms mge = 0 2.5 2.8 3.1 v p-p mge = 1 0.29 0.36 0.43 v p-p input impedance 100 k w input capacitance 15 pf programmable gain amplifieradc min typ max units step size (0 db to 22.5 db) 1.0 1.5 2.0 db (all steps tested) pga gain range span 21.0 22.5 24.0 db auxiliary input analog amplifiers/attenuators min typ max units step size (+12 db to C28.5 db, referenced to dac full scale) 1.3 1.5 1.7 db (C30 db to C34.5 db, referenced to dac full scale) 1.0 1.5 2.0 db auxiliary gain/attenuation range span 45.5 46.5 47.5 db auxiliary input impedance* 10 k w
digital decimation and interpolation filters* min max units passband 0 0.4 3 f s hz passband ripple 0.1 db transition band 0.4 3 f s 0.6 3 f s hz stopband 0.6 3 f s hz stopband rejection 74 db group delay 30/f s group delay variation over passband 0.0 m s analog-to-digital converters min typ max units resolution 16 bits dynamic range (C60 db input, 70 75 db thd+n referenced to full scale, a-weighted) thd+n (referenced to full scale) 0.02 % C72 C70 db signal-to-intermodulation distortion 83 db adc crosstalk* line inputs (input l, ground r, read r; C80 db input r, ground l, read l) line to mic (input line, ground and C80 db select mic, read both channels) line to aux1 C80 db line to aux2 C80 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch 0.5 db (difference of gain errors) adc offset error 12 mv digital-to-analog converters min typ max units resolution 16 bits dynamic range (C60 db input, 80 83 db thd+n referenced to full scale, a-weighted) thd+n (referenced to full scale) 0.02 % C73 C70 db signal-to-intermodulation distortion 86 db gain error (full-scale span relative to nominal output voltage) 10 % interchannel gain mismatch 0.5 db (difference of l and r gain errors) dac crosstalk* (input l, zero r, measure C80 db r_out; input r, zero l, measure l_out) total out-of-band energy* C50 db (measured from 0.6 3 f s to 96 khz) audible out-of-band energy* C70 db (measured from 0.6 3 f s to 20 khz, tested at 5.5 khz) *guaranteed not tested. specifications subject to change without notice. AD1846 rev. a C3C
AD1846 rev. a C4C dac attenuator min typ max units step size (0 db to C60 db) 1.3 1.5 1.7 db (tested at steps 0 db, C19.5 db and C60 db) step size (C60 db to C94.5 db)* 1.0 1.5 2.0 db output attenuation range span* 93.5 94.5 95.5 db analog output min typ max units full-scale output voltage 0.707 v rms 1.8 2.0 2.2 v p-p output impedance* 600 w external load impedance 10 k w output capacitance* 15 pf external load capacitance 100 pf v ref 2.00 2.25 2.50 v v ref current drive 100 m a v ref output impedance 4 k w mute attenuation of 0 db C80 db fundamental* (out) mute click 5mv (|muted output minus unmuted midscale dac output|) system specifications min typ max units peak-to-peak frequency response ripple* 1.0 db (line in to line out) differential nonlinearity* 1 bit phase linearity deviation* 5 degrees static digital specifications min max units high level input voltage (v ih ) digital inputs 2.4 (v dd ) + 0.3 v xtal1/2i 2.4 (v dd ) + 0.3 v low level input voltage (v il ) C0.3 0.8 v high level output voltage (v oh ) at i oh = C2 ma 2.4 v low level output voltage (v ol ) at i ol = 2 ma 0.4 v input leakage current C10 10 m a (go/nogo tested) output leakage current C10 10 m a (go/nogo tested) digital mix attenuator min typ max units step size (0 db to C94 db) (tested at steps 0 db, C19.5 db) 1.0 1.5 2.0 db output attenuation range span* C93.5 95.5 db *guaranteed, not tested.
timing parameters (guaranteed over operating temperature range) min max units wr / rd strobe width (t stw ) 130 ns wr / rd rising to wr / rd falling (t bwnd ) 140 ns write data setup to wr rising (t wdsu )10 ns rd falling to valid read data (t rddv )2040ns cs setup to wr / rd falling (t cssu )10 ns cs hold from wr / rd rising (t cshd )0 ns adr setup to wr / rd falling (t adsu )10 ns adr hold from wr / rd rising (t adhd )10 ns dak rising to wr / rd falling (t sudk1 )60 ns dak falling to wr / rd rising (t sudk2 )0 ns dak setup to wr / rd falling (t dksu )25 ns data hold from rd rising (t dhd1 )020ns data hold from wr rising (t dhd2 )15 ns drq hold from wr / rd falling (t drhd )030ns dak hold from wr rising (t dkhda )10 ns dak hold from rd rising (t dkhdb )10 ns dben /dbdir delay from wr / rd falling (t dbdl )0 20 ns power supply min max units power supply range C analog 4.75 5.25 v power supply range C 5 v digital 4.75 5.25 v power supply current C 5 v operating 120 ma (5 v supplies) analog supply current C 5 v operating 65 ma digital supply current C 5 v operating 55 ma digital power supply current C power down 0.5 ma analog power supply current C power down 0.5 ma power dissipation C 5 v operating 600 mw (current ? nominal supplies) power dissipation C power down (current ? nominal supplies) 5 mw power supply rejection (100 mv p-p signal @ 1 khz)* 40 db (at both analog and digital supply pins, both adcs and dacs) clock specifications* min max units input clock frequency 27 mhz recommended clock duty cycle tolerance 10 % initialization time 16.9344 mhz crystal selected 70 ms 24.576 mhz crystal selected 90 ms *guaranteed, not tested. specifications subject to change without notice. AD1846 rev. a C5C
AD1846 rev. a C6C ordering guide temperature package model range description AD1846jp 0 c to +70 c 68-lead plcc absolute maximum ratings* min max units power supplies digital (v dd ) C0.3 6.0 v analog (v cc ) C0.3 6.0 v input current (except supply pins) 10.0 ma analog input voltage (signal pins) C0.3 (v cc ) + 0.3 v digital input voltage (signal pins) C0.3 (v dd ) + 0.3 v ambient temperature (operating) 0 +70 c storage temperature C65 +150 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1846 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 68-lead plastic leaded chip carrier pinout 67 66 65 68 1 2 3 63 62 61 64 54 6 7 8 9 16 17 18 19 20 21 22 23 24 25 26 10 11 12 13 14 15 37 38 39 35 34 33 41 42 43 40 31 32 30 29 28 27 53 52 51 50 49 48 47 46 45 44 60 59 58 57 56 55 36 54 rd xctl1 int xctl0 nc v dd gndd nc v dd gndd cs nc nc nc nc nc nc adr1 v dd data0 data1 data2 data3 gndd v dd dbdir gndd data4 data5 data6 data7 gndd wr dben adr0 cdrq pdrq v dd gndd xtal1i xtal1o gndd r_filt v dd gndd xtal2i xtal2o v dd pwrdwn pdak cdak r_line l_mic l_line l_filt v ref (2.25v) v ref _f (bypass) gnda v cc r_aux1 r_mic gnda l_aux2 l_aux1 l_out r_aux2 r_out v cc AD1846 top view nc = no connect
AD1846 rev. a C7C pin description parallel interface pin name plcc i/o description cdrq 12 o capture data request. the assertion of this signal indicates that the codec has a captured audio sample from the adc ready for transfer. this signal will remain asserted until all the bytes from the capture buffer have been transferred. cdak 11 i capture data acknowledge. the assertion of this active lo signal indicates that the rd cycle occurring is a dma read from the capture buffer. pdrq 14 o playback data request. the assertion of this signal indicates that the codec is ready for more dac playback data. the signal will remain asserted until all the bytes needed for a playback sample have been transferred. pdak 13 i playback data acknowledge. the assertion of this active lo signal indicates that the wr cycle occurring is a dma write to the playback buffer. adr1:0 9 & 10 i codec addresses. these address pins are asserted by the codec interface logic during a con- trol register/pio access. the state of these address lines determine which register is accessed. rd 60 i read command strobe. this active lo signal defines a read cycle from the codec. the cycle may be a read from the control/pio registers, or the cycles could be a read from the codecs dma sample registers. wr 61 i write command strobe. this active lo signal indicates a write cycle to the codec. the cycle may be a write to the control/pio registers, or the cycle could be a write to the codecs dma sample registers. cs 59 i AD1846 chip select. the codec will not respond to any control/pio cycle accesses unless this active lo signal is lo. this signal is ignored during dma transfers. data7:0 3C6 & i/o data bus. these pins transfer data and control information between the codec and the host. 65C68 dben 63 o data bus enable. this pin enables the external bus drivers. this signal is normally hi. for control register/pio cycles, dben = ( wr or rd ) and cs for dma cycles, dben = ( wr or rd ) and ( pdak or cdak ) dbdir 62 o data bus direction. this pin controls the direction of the data bus transceiver. hi enables writes from the host to the AD1846; lo enables reads from the AD1846 to the host bus. this signal is normally hi. for control register/pio cycles, dbdir = rd and cs for dma cycles, dbdir = rd and ( pdak or cdak )
AD1846 rev. a C8C analog signals pin name plcc i/o description l_line 30 i left line input. line level input for the left channel. r_line 27 i right line input. line level input for the right channel. l_mic 29 i left microphone input. microphone input for the left channel. this signal can be ei- ther line level or C20 db from line level. r_mic 28 i right microphone input. microphone input for the right channel. this signal can be either line level or C20 db from line level. l_aux1 39 i left auxiliary #1 line input r_aux1 42 i right auxiliary #1 line input l_aux2 38 i left auxiliary #2 line input r_aux2 43 i right auxiliary #2 line input l_out 40 o left line level output r_out 41 o right line level output miscellaneous pin name plcc i/o description xtal1i 17 i 24.576 mhz crystal #1 input xtal1o 18 o 24.576 mhz crystal #1 output xtal2i 21 i 16.9344 mhz crystal #2 input xtal2o 22 o 16.9344 mhz crystal #2 output pwrdwn 23 i power-down signal. active lo control places AD1846 in its lowest power consump- tion mode. all sections of the AD1846, including the digital interface, are shut down and consume minimal power. int 57 o host interrupt pin. this signal is used to notify the host that the dma current count register has underflowed. xctl1:o 56 & 58 o external control. these signals reflect the current status of register bits inside the AD1846. they can be used for signaling or to control external logic. xltl1 and xltl0 are open-drain outputs. v ref 32 o voltage reference. nominal 2.25 volt reference available externally for dc-coupling and level-shifting. v ref should not be used where it will sink or source current. v ref _f 33 i voltage reference filter. voltage reference filter point for external bypassing only. l_filt 31 i left channel filter input. this pin requires a 1.0 m f capacitor to analog ground for proper operation. r_filt 26 i right channel filter input. this pin requires a 1.0 m f capacitor to analog ground for proper operation. nc 46C52, 55 no connect. do not connect. power supplies pin name plcc i/o description v cc 35 & 36 i analog supply voltage (+5 v) gnda 34 & 37 i analog ground v dd 1, 7, 15, 19, i digital supply voltage (+5 v) 24, 45, 54 gndd 2, 8, 16, 20, i digital ground 25, 44, 53, 64
AD1846 rev. a C9C (continued from page 1) 8 7 4 2 4 5 dir g aen sa19:2 sa1 sa0 iowc iorc data7:0 address decode drq drq dak dak irq a b isa bus 8 18 cs a1 a0 wr rd data7:0 dbdir dben pdrq cdrq pdak cdak int AD1846 figure 1. interface to isa bus the pair of 16-bit outputs from the adcs is available over a byte-wide bidirectional interface that also supports 16-bit digital input to the dacs and control information. the AD1846 can accept and generate 16-bit twos-complement pcm linear digital data, 8-bit unsigned magnitude pcm linear data, and 8-bit m -law or a-law companded digital data. the ?d dacs are preceded by a digital interpolation filter. an attenuator provides independent user volume control over each dac channel. nyquist images and shaped quantization noise are removed from the dacs analog stereo output by on-chip switched-capacitor and continuous-time filters. two stereo pairs of auxiliary line-level inputs can also be mixed in the analog do- main with the dac output. audio functional description this section overviews the functionality of the AD1846 and is intended as a general introduction to the capabilities of the de- vice. as much as possible, detailed reference information has been placed in control registers and other sections. the user is not expected to refer repeatedly to this section. analog inputs the AD1846 soundport stereo codec accepts stereo line-level and mic-level inputs. line, mic, and aux1 inputs and post- mixed dac output analog stereo signals are multiplexed to the internal programmable gain amplifier (pga) stage. the pga following the input multiplexer allows independent selectable gains for each channel from 0 to 22.5 db in +1.5 db steps. the codec can operate either in a global stereo mode or in a global mono mode with left channel inputs appearing at both channel outputs. analog mixing aux1 and aux2 analog stereo signals can be mixed in the ana- log domain with the dac output. each channel of each auxil- iary analog input can be independently gained/attenuated from +12 db to C34.5 db in C1.5 db steps or completely muted. the post mixed dac output is available on out externally and as an input to the adcs. even if the AD1846 is not playing back data from its dacs, the analog mix function can still be active. analog-to-digital datapath the AD1846 ?d adcs incorporate a fourth order modulator. a single pole of passive filtering is all that is required for anti- aliasing the analog input because of the adcs high 64 times oversampling ratio. the adcs include linear phase digital deci- mation filters that low-pass filter the input to 0.4 3 f s . (f s is the word rate or sampling frequency). adc input overrange conditions will cause bits to be set that can be read. each channel of the mic inputs can be amplified digitally by +18 db to compensate for the voltage swing differences between line levels and typical condenser microphone levels. this +18 db digital gain is enabled with the same control bits (lmge and rmge) as the +20 db analog gain in the ad1848. digital-to-analog datapath the ?d dacs contain a programmable attenuator and a low- pass digital interpolation filter. the anti-imaging interpolation filter oversamples by 64 and digitally filters the higher frequency images. the attenuator allows independent control of each dac channel from 0 db to C94.5 db in 1.5 db steps plus full mute. the dacs ?d noise shapers also oversample by 64 and convert the signal to a single bit stream. the dac outputs are then filtered in the analog domain by a combination of switched- capacitor and continuous-time filters. they remove the very high frequency components of the dac bitstream output. no external components are required. phase linearity at the analog output is achieved by internally compensating for the group delay variation of the analog output filters. changes in dac output attenuation take effect only on zero crossings, thereby eliminating zipper noise. each channel has its own independent zero-crossing detector and attenuator change control circuitry. a timer guarantees that requested vol- ume changes will occur even in the absence of an input signal that changes sign. the time-out period is 8 milliseconds at a 48 khz sampling rate and 48 milliseconds at an 8 khz sampling rate. (time out [ms] ? 384/f s [khz].) digital mixing stereo digital output from the adcs can be mixed digitally with the input to the dacs. digital output from the adcs going out of the data port is unaffected by the digital mix. along the digi- tal mix datapath, the 16-bit linear output from the adcs is attenuated by an amount specified with control bits. both chan- nels of the monitor data are attenuated by the same amount. (note that internally the AD1846 always works with 16-bit pcm linear data, digital mixing included; format conversions take place at the input and output.)
AD1846 rev. a C10C sixty-four steps of C1.5 db attenuation are supported to C94.5 db. the digital mix datapath can also be completely muted, preventing any mixing of the analog input with the digi- tal input. note that the level of the mixed signal is also a func- tion of the input pga settings, since they affect the adcs output. the attenuated digital mix data is digitally summed with the dac input data prior to the dacs datapath attenuators. the digital sum of digital mix data and dac input data is clipped at plus or minus full scale and does not wrap around. because both stereo signals are mixed before the output attenuators, mix data is attenuated a second time by the dacs datapath attenuators. in case the AD1846 is capturing data but adc output data is not removed in time (adc overrun), then the last sample captured before overrun will be used for the digital mix. in case the AD1846 is playing back data hut input digital dac data fails to arrive in time (dac underrun), then a midscale zero will be added to the digital mix data. analog outputs a stereo line level output is available at external pins. each channel of this output can be independently muted. when muted, the outputs will settle to a dc value near v ref , the midscale reference voltage. digital data types the AD1846 supports four data types: 16-bit twos-complement linear pcm, eight-bit unsigned linear pcm, companded m -law, and 8-bit companded a-law, as specified by control register bits. data in all four formats is always transferred msb first. stereo data is always transferred in the left-right order. all data formats that are less than 16 bits are properly aligned to insure the utili- zation of full system resolution. the 16-bit pcm data format is capable of representing 96 db of dynamic range. eight-bit pcm can represent 48 db of dynamic range. companded m -law and a-law data formats use nonlinear coding with less precision for large amplitude signals. the loss of precision is compensated for by an increase in dynamic range to 64 db and 72 db, respectively. on input, 8-bit companded data is expanded to an internal lin- ear representation, according to whether m -law or a-law was specified in the codecs internal registers. note that when m -law compressed data is expanded to a linear format, it requires 14 bits. a-law data expanded requires 13 bits. 3/2 2/1 15 0 15 0 msb msb 0 0 0 / 0 0 15 0 msb dac input expansion compressed input data 3/2 2/1 lsb lsb 8 7 lsb figure 2. a-law or m -law expansion when 8-bit companding is specified, the adcs linear output is compressed to the format specified. lsb 3/2 2/1 15 0 15 0 msb msb 0 0 0 0 0 0 0 0 15 0 msb adc output truncation compression lsb 8 7 lsb figure 3. a-law or m -law compression note that all format conversions take place at input or output. internally, the AD1846 always uses 16-bit linear pcm represen- tations to maintain maximum precision. power supplies and voltage reference the AD1846 operates from +5 v power supplies. independent analog and digital supplies are recommended for optimal perfor- mance though excellent results can be obtained in single supply systems. a voltage reference is included on the codec and its 2.25 v buffered output is available on an external pin (v ref ). the reference output can be used for biasing op amps used in dc coupling. the internal reference must be externally bypassed to analog ground at the v ref _f pin. clocks and sample rates the AD1846 operates from external crystals. two crystal inputs are provided to generate a wide range of sample rates. the oscil- lators for these crystals are on the AD1846, as is a multiplexer for selecting between them. they can be overdriven with exter- nal clocks by the user, if so desired. the recommended crystal frequencies are 16.9344 mhz and 24.576 mhz. from them the following sample rates are divided down: 5.5125, 6.615, 8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48 khz.
AD1846 rev. a C11C index register name 0 left input control 1 right input control 2 left aux #1 input control 3 right aux #1 input control 4 left aux #2 input control 5 right aux #2 input control 6 left output control 7 right output control 8 clock and data format 9 interface configuration 10 pin control 11 test and initialization 12 miscellaneous information 13 digital mix 14 upper base count 15 lower base count control registers control register architecture the AD1846 soundport stereo codec accepts both data and control information through its byte-wide parallel port. indirect addressing minimizes the number of external pins required to access all 21 of its byte-wide internal registers. only two exter- nal address pins, adr1:0, are required to accomplish all data and control transfers. these pins select one of five direct regis- ters. (adr1:0 = 3 addresses two registers, depending on whether the transfer is a playback or a capture.) adr1:0 register name 0 index address register 1 indexed data register 2 status register 3 pio data registers figure 4. direct register map a write to or a read from the indexed data register will access the indirect register which is indexed by the value most recently written to the index address register. the status register and the pio data register are always accessible directly, without in- dexing. the 16 indirect registers are indexed in figure 5. direct registers: adr1:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0 init mce trd res ixa3 ixa2 ixa1 ixa0 1 ixd7 ixd6 ixd5 ixd4 ixd3 ixd2 ixd1 ixd0 2 cu/l cl/r crdy sour pu/l pl/r prdy int 3 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 indirect registers: ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0 lss1 lss0 lmge res lig3 lig2 lig1 lig0 1 rss1 rss0 rmge res rig3 rig2 rig1 rig0 2 lmx1 res res lx1a4 lx1a3 lx1a2 lx1a1 lx1a0 3 rmx1 res res rx1a4 rx1a3 rx1a2 rx1a1 rx1a0 4 lmx2 res res lx2a4 lx2a3 lx2a2 lx2a1 lx2a0 5 rmx2 res res rx2a4 rx2a3 rx2a2 rx2a1 rx2a0 6 ldm res lda5 lda4 lda3 lda2 lda1 lda0 7 rdm res rda5 rda4 rda3 rda2 rda1 rda0 8 res fmt c/l s/m cfs2 cfs1 cfs0 css 9 cpio ppio res res acal sdc cen pen 10 xctl1 xctl0 res res res res ien res 11 cor pur aci drs orr1 orr0 orl1 orl0 12 res res res res id3 id2 id1 id0 13 dma5 dma4 dma3 dma2 dma1 dma0 res dme 14 ub7 ub6 ub5 ub4 ub3 ub2 ub1 ub0 15 lb7 lb6 lb5 lb4 lb3 lb2 lb1 lb0 figure 6. register summary note that the only sticky bit in any of the AD1846 control registers is the interrupt (int) bit. all other bits change with every sample period. figure 5. indirect register map a detailed map of all direct and indirect register contents is summarized for reference as follows:
AD1846 rev. a C12C direct control register definitions index register (adr1:0 = 0) adr1:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0 init mce trd res ixa3 ixa2 ixa1 ixa0 ixa3:0 index address. these bits define the address of the AD1846 register accessed by the indexed data register. these bits are read/write. res reserved for future expansion. always write a zero to this bit. trd transfer request disable. this bit, when set, causes all data transfers to cease when the interrupt status (int) bit of the status register is set. 0 transfers enabled during interrupt. pdrq and cdrq pin outputs are generated uninhibited by interrupts. dma current counter register decrements with every sample period when either pen or cen are enabled. 1 transfers disabled by interrupt. pdrq and cdrq pin outputs are generated only if int bit is 0 (when either pen or cen, respectively, are enabled). any pending playback or capture requests are allowed to complete at the time when trd is set. after pending requests complete, midscale inputs will be internally generated for the dacs, and the adc output buffer will contain the last valid output. clearing the sticky int bit (or the trd bit) will cause the resumption of playback and/or capture requests (presuming pen and/or cen are enabled). the dma current counter register will not decrement while both the trd bit is set and the int bit is a one. mce mode change enable. this bit must be set whenever the current functional mode of the AD1846 is changed. specifically, the clock and data format and interface configuration registers cannot be changed unless this bit is set. the exceptions are cen and pen in the interface configuration which can be changed on-the-fly. mce should be cleared at the com- pletion of the desired register changes. the dac outputs are automatically muted when the mce bit is set. after mce is cleared, the dac outputs will be restored to the state specified by the ldm and rdm mute bits. both adcs and dacs are automatically muted for approximately 128 sample cycles after exiting the mce state to allow the reference and all filters to settle. the adcs will produce midscale values; the dacs analog output will be muted. all converters are internally operating during these ? 128 sample cycles, and the AD1846 will expect playback data and will generate (midscale) capture data. note that the autocalibrate-in-process (aci) bit will be set on exit from the mce state regardless of whether or not acal was set. aci will remain hi for these ? 128 sample cycles; system software should poll this bit rather than count cycles. special sequences must be followed if autocalibrate (acal) is set or sample rates are changed (cfs2:0 and or css) during mode change enable. see the autocalibration and changing sample rates sections below. init AD1846 initialization. this bit is set when the AD1846 is in a state which cannot respond to parallel bus cycles. this bit is read only. immediately after reset and once the AD1846 has left the init state, the initial value of this register will be 0100 0000 (40h). during AD1846 initialization, this register cannot be written to and will always read 100x 0000 (80h). indexed data register (adr1:0 = 1) adr1:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 1 ixd7 ixd6 ixd5 ixd4 ixd3 ixd2 ixd1 ixd0 ixd7:0 indexed register data. these bits contain the contents of the AD1846 register referenced by the indexed data register. during AD1846 initialization, this register cannot be written to and will always read as 1000 0000 (80h).
AD1846 rev. a C13C status register (adr1:0 = 2) adr1:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 2 cu/l cl/r crdy sour pu/l pl/r prdy int int interrupt status. this sticky bit (the only one) indicates the status of the interrupt logic of the AD1846. this bit is cleared by any host write of any value to this register. the ien bit of the pin control register determines whether the state of this bit is reflected on the int pin of the AD1846. the only interrupt condition supported by the AD1846 is generated by the underflow of the dma current count register. 0 interrupt pin inactive 1 interrupt pin active prdy playback data register ready. the pio playback data register is ready for more data. this bit should only be used when direct programmed i/o data transfers are desired. this bit is read only. 0 dac data is still valid. do not overwrite. 1 dac data is stale. ready for next host data write value. pl/r playback left/right sample. this bit indicates whether the pio playback data needed is for the right channel dac or left channel dac. this bit is read only. 0 right channel needed 1 left channel or mono pu/l playback upper/lower byte. this bit indicates whether the pio playback data needed is for the upper or lower byte of the channel. this bit is read only. 0 lower byte needed 1 upper byte needed or any 8-bit mode sour sample over/underrun. this bit indicates that the most recent sample was not serviced in time and therefore either a cap- ture overrun (cor) or playback underrun (pur) has occurred. the bit indicates an overrun for adc capture and an underrun for dac playback. if both capture and playback are enabled, the source which set this bit can be determined by reading cor and pur. this bit changes on a sample-by-sample basis. this bit is read only. crdy capture data ready. the pio capture data register contains data ready for reading by the host. this bit should only be used when direct programmed i/o data transfers are desired. this bit is read only. 0 adc data is stale. do not reread the information. 1 adc data is fresh. ready for next host data read. cl/r capture left/right sample. this bit indicates whether the pio capture data waiting is for the right channel adc or left channel adc. this bit is read only. 0 right channel 1 left channel or mono cu/l capture upper/lower byte. this bit indicates whether the pio capture data ready is for the upper or lower byte of the channel. this bit is read only. 0 lower byte ready 1 upper byte ready or any 8-bit mode the prdy, crdy, and int bits of this status register can change asynchronously to host accesses. the host may access this regis- ter while the bits are transitioning. the host read may return a zero value just as these bits are changing, for example. a 1 value would not be read until the next host access. this registerss initial state after reset is 1100 1100.
AD1846 rev. a C14C pio data registers (adr1:0 = 3) adr1:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 3 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 the pio data registers are two registers mapped to the same address. writes send data to the pio playback data register (pd7:0). reads will receive data from the pio capture data register (cd7:0). during AD1846 initialization, the pio playback data register cannot be written and the capture data register is always read 1000 0000 (80h). cd7:0 pio capture data register. this is the control register where capture data is read during programmed i/o data transfers. the reading of this register will increment the state machine so that the following read will be from the next appropriate byte in the sample. the exact byte which is next to be read can be determined by reading the status register. once all rel- evant bytes have been read, the state machine will stay pointed to the last byte of the sample until a new sample is received from the adcs. once this has occurred, the state machine and status register will point to the first byte of the sample. until a new sample is received, reads from this register will return the most significant byte of the sample. pd7:0 pio playback data register. this is the control register where playback data is written during programmed i/o data transfers. writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the sample. once all bytes of a sample have been written, subsequent byte writes to this port are ig- nored. the state machine is reset when the current sample is sent to the dacs. indirect control register definitions the following control registers are accessed by writing index values to ixa3:0 in the index address register (adr1:0 = 0) followed by a read/write to the indexed data register (adr1:0 = 1). left input control (ixa3:0 = 0) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0 lss1 lss0 lmge res lig3 lig2 lig1 lig0 lig3:0 left input gain select. the least significant bit of this gain select represents +1.5 db. maximum gain is +22.5 db. res reserved for future expansion. always write a zero to this bit. lmge left input microphone gain enable. setting this bit will enable the +18 db digital gain of the left mic input signal. lss1:0 left input source select. these bits select the input source for the left gain stage preceding the left adc. 0 left line source selected 1 left auxiliary 1 source selected 2 left microphone source selected 3 left line post-mixed dac output source selected this registers initial state after reset is 000x 0000.
AD1846 rev. a C15C right input control (ixa3:0 = 1) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 1 rss1 rss0 rmge res rig3 rig2 rig1 rig0 rig3:0 right input gain select. the least significant bit of this gain select represents +1.5 db. maximum gain is +22.5 db. res reserved for future expansion. always write a zero to this bit. rmge right input microphone gain enable. setting this bit will enable the +18 db digital gain of the right mic input signal. rss1:0 right input source select. these bits select the input source for the right channel gain stage preceding the right adc. 0 right line source selected 1 right auxiliary 1 source selected 2 right microphone source selected 3 right post-mixed dac output source selected this registers initial state after reset is 000x 0000. left auxiliary #1 input control (ixa3:0 = 2) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 2 lmx1 res res lx1a4 lx1a3 lx1a2 lx1a1 lx1a0 lx1a4:0 left auxiliary input #1 attenuate select. the least significant bit of this gain/attenuate select represents C1.5 db. lx1a4:0 = 0 produces a +12 db gain. lx1a4:0 = 01000 (8 decimal) produces 0 db gain. maximum attenuation is C34.5 db. res reserved for future expansion. always write zeros to these bits. lmx1 left auxiliary #1 mute. this bit, when set, will mute the left channel of the auxiliary #1 input source. this bit is set to 1 after reset. this registers initial state after reset is 1xx0 0000. right auxiliary #1 input control (ixa3:0 = 3) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 3 rmx1 res res rx1a4 rx1a3 rx1a2 rx1a1 rx1a0 rx1a4:0 right auxiliary input #1 attenuate select. the least significant bit of this gain/attenuate select represents C1.5 db. rx1a4:0 = 0 produces a +12 db gain. rx1a4:0 = 01000 (8 decimal) produces 0 db gain. maximum attenuation is C34.5 db. res reserved for future expansion. always write zeros to these bits. rmx1 right auxiliary #1 mute. this bit, when set, will mute the right channel of the auxiliary #1 input source. this bit is set to 1 after reset. this registers initial state after reset is 1xx0 0000.
AD1846 rev. a C16C left auxiliary #2 input control (ixa3:0 = 4) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 4 lmx2 res res lx2a4 lx2a3 lx2a2 lx2a1 lx2a0 lx2a4:0 left auxiliary input #2 attenuate select. the least significant bit of this gain/attenuate select represents C1.5 db. lx2a4:0 = 0 produces a +12 db gain. lx2a4:0 = 01000 (8 decimal) produces 0 db gain. maximum attenuation is C34.5 db. res reserved for future expansion. always write zeros to these bits. lmx2 left auxiliary #2 mute. this bit, when set to 1, will mute the left channel of the auxiliary #2 input source. this bit is set to 1 after reset. this registers initial state after reset is 1xx0 0000. right auxiliary #2 input control (ixa3:0 = 5) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 5 rmx2 res res rx2a4 rx2a3 rx2a2 rx2a1 rx2a0 rx2a4:0 right auxiliary input #2 attenuate select. the least significant bit of this gain/attenuate select represents C1.5 db. rx2a4:0 = 0 produces a +12 db gain. rx2a4:0 = 01000 (8 decimal) produces 0 db gain. maximum attenuation is C34.5 db. res reserved for future expansion. always write zeros to these bits. rmx2 right auxiliary #2 mute. this bit, when set, will mute the right channel of the auxiliary #2 input source. this bit is set to 1 after reset. this registers initial state after reset is 1xx0 0000. left dac control (ixa3:0 = 6) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 6 ldm res lda5 lda4 lda3 lda2 lda1 lda0 lda5:0 left dac attenuate select. the least significant bit of this attenuate select represents C1.5 db. lda5:0 = 0 produces a 0 db attenuation. maximum attenuation is C94.5 db. res reserved for future expansion. always write a zero to this bit. ldm left dac mute. this bit, when set to 1, will mute the left dac output. auxiliary inputs are muted independently with the left auxiliary input control registers. this bit is set to 1 after reset. this registers initial state after reset is 1x00 0000. right dac control (ixa3:0 = 7) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 7 rdm res rda5 rda4 rda3 rda2 rda1 rda0 rda5:0 right dac attenuate select. the least significant bit of this attenuate select represents C1.5 db. rda5:0 = 0 produces 0 db attenuation. maximum attenuation is C94.5 db. res reserved for future expansion. always write a zero to this bit. rdm right dac mute. this bit, when set to 1, will mute the right dac output. auxiliary inputs are muted independently with the right auxiliary input control registers. this bit is set to 1 after reset. this registers initial state after reset is 1x00 0000.
AD1846 rev. a C17C clock and data format register (ixa3:0 = 8) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 8 res fmt c/l s/m cfs2 cfs1 cfs0 css the contents of the clock and data format register cannot be changed except when the AD1846 is in mode change enable (mce) state. write attempts to this register when the AD1846 is not in the mce state will not be successful. css clock source select. these bits select the crystal clock source which will be used for the audio sample rates. 0 xtal1 (24.576 mhz) 1 xtal2 (16.9344 mhz) cfs2:0 clock frequency divide select. these bits select the audio sample rate frequency. the actual audio sample rate depends on which crystal clock source is selected and the frequency of that source. divide xtal1 xtal2 cfs factor 24.576 mhz 16.9344 mhz 0 3072 8.0 khz 5.5125 khz 1 1536 16.0 khz 11.025 khz 2 896 27.42857 khz 18.9 khz 3 768 32.0 khz 22.05 khz 4 448 not supported 37.8 khz 5 384 not supported 44.1 khz 6 512 48.0 khz 33.075 khz 7 2560 9.6 khz 6.615 khz note that the AD1846s internal oscillators can be driven by external clock sources at the crystal input pins. if an external clock source is applied, it will be divided down by the selected divide factor. it need not be at the recommended crystal frequencies. s/m stereo/mono select. this bit determines how the audio data streams are formatted. selecting stereo will result with alter- nating samples representing left and right audio channels. mono playback plays the same audio sample on both channels. mono capture only captures data from the left audio channel. 0 mono 1 stereo c/l companded/linear select. this bit selects between a linear digital representation of the audio signal or a nonlinear, com- panded format for all input and output data. the type of linear pcm or the type of companded format is defined by the fmt bits. 0 linear pcm 1 companded fmt format select. this bit defines the format for all digital audio input and outputs based on the state of the c/l bit. linear pcm (c/l = 0) companded (c/l = 1) 0 8-bit unsigned pcm 8-bit m -law companded 1 16-bit twos-complement pcm 8-bit a-law companded res reserved for future expansion. always write a zero to this bit. this registers initial state after reset is x000 0000.
AD1846 rev. a C18C interface configuration register (ixa3:0 = 9) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 9 cpio ppio res res acal sdc cen pen the contents of the interface configuration register cannot be changed except when the AD1846 is in mode change enable (mce) state. write attempts to this register when the AD1846 is not in the mce state will not be successful. pen and cen are exceptions; these bits may al- wa ys be written. pen playback enable. this bit will enable the playback of data in the format selected. the AD1846 will generate pdrq and respond to pdak signals when this bit is enabled and ppio = 0. if ppio = 1, this bit enables programmed i/o (pio) playback mode. pen may be set and reset without setting the mce bit. 0 playback disabled (pdrq and pio playback data register inactive) 1 playback enabled cen capture enable. this bit will enable the capture of data in the format selected. the AD1846 will generate cdrq and re- spond to cdak signals when this bit is enabled and cpio = 0. if cpio = 1, this bit enables pio capture mode. cen may be set and reset without setting the mce bit. 0 capture disabled (cdrq and pio capture data register inactive) 1 capture enabled sdc single dma channel. this bit will force both capture and playback dma requests to occur on the playback dma chan- nel. the capture dma cdrq pin will be lo. this bit will allow the AD1846 to be used with only one dma channel. simultaneous capture and playback cannot occur in this mode. should both capture and playback be enabled (cen = pen = 1) in the mode, only playback will occur. see data and control transfers for further explanation. 0 dual dma channel mode 1 single dma channel mode acal autocalibrate enable. this bit determines whether the AD1846 performs an autocalibrate whenever the pwrdwn pin is deasserted or from the mode change enable (mce) bit being reset. acal is normally set. see autocalibration below for a description of a complete autocalibration sequence. 0 no autocalibration 1 autocalibration after power down/reset or mode change res reserved for future expansion. always write zeros to these bits. ppio playback pio enable. this bit determines whether the playback data is transferred via dma or pio. 0 dma transfers only 1 pio transfers only cpio capture pio enable. this bit determines whether the capture data is transferred via dma or pio. 0 dma transfers only 1 pio transfers only this registers initial state after reset is 00xx 1000. pin control register (ixa3:0 = 10) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 10 xctl1 xctl0 res res res res ien res res reserved for future expansion. always write zeros to these bits. ien interrupt enable. this bit enables the interrupt pin. the interrupt pin will go active hi when the number of samples pro- grammed in the base count register is reached. 0 interrupt disabled 1 interrupt enabled xctl1:0 external control. the state of these independent bits is reflected on the respective xctl1:0 pins of the AD1846. 0 ttl logic lo on xctl1:0 pins 1 ttl logic hi on xctl1:0 pins this registers initial state after reset is 00xx xx0x.
AD1846 rev. a C19C test and initialization register (ixa3:0 = 11) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 11 cor pur aci drs orr1 orr0 orl1 orl0 orl1:0 overrange left detect. these bits indicate the overrange on the left input channel. this bit changes on a sample-by- sample basis. this bit is read only. 0 less than C1 db underrange 1 between C1 db and 0 db underrange 2 between 0 db and +1 db overrange 3 greater than +1 db overrange orr1:0 overrange right detect. these bits indicate the overrange on the right input channel. this bit changes on a sample-by- sample basis. this bit is read only. 0 less than C1 db underrange 1 between C1 db and 0 db underrange 2 between 0 db and +1 db overrange 3 greater than +1 db overrange drs data request status. this bit indicates the current status of the pdrq and cdrq pins of the AD1846. 0 cdrq and pdrq are presently inactive (lo) 1 cdrq or pdrq are presently active (hi) aci autocalibrate-in-progress. this bit indicates the state of autocalibration or a recent exit from mode change enable (mce). this bit is read only. 0 autocalibration is not in progress 1 autocalibration is in progress or mce was exited within approximately the last 128 sample periods pur playback underrun. this bit is set when playback data has not arrived from the host in time to be played. as a result, a midscale value will be sent to the dacs. this bit changes on a sample by sample basis. cor capture overrun. this bit is set when the capture data has not been read by the host before the next sample arrives. the sample being read will not be overwritten by the new sample. the new sample will be ignored. this bit changes on a sample by sample basis. the occurrence of a pur and/or cor is designated in the status registers sample overrun/underrun (sour) bit. the sour bit is the logical or of the cor and pur bits. this enables a polling host cpu to detect an overrun/underrun condition while checking other status bits. this registers initial state after reset is 0000 0000. miscellaneous control register (ixa3:0 = 12) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 12 res res res res id3 id2 id1 id0 res reserved for future expansion. the bits are read only. do not write to these bits. id3:0 AD1846 revision id. these four bits define the revision level of the AD1846. the AD1846 is designated id = 1010. revisions increment by one lsb. these bits are read only. this registers initial state after reset is xxxx rrrr where rrrr = revision id of the silicon in use.
AD1846 rev. a C20C digital mix control register (ixa3:0 = 13) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 13 dma5 dma4 dma3 dma2 dma1 dma0 res dme dme digital mix enable. this bit will enable the digital mix of the adcs output with the dacs input. when enabled, the data from the adcs are digitally mixed with other data being delivered to the dacs (regardless of whether or not play- back [pen] is enabled, i.e., set). if capture is enabled (cen set) and there is a capture overrun (cor), then the last sample captured before overrun will be used for the digital mix. if playback is enabled (pen set) and there is a playback underrun (pur), then a midscale zero will be added to the digital mix data. 0 digital mix disabled (muted) 1 digital mix enabled res reserved for future expansion. always write a zero to this bit. dma5:0 digital mix attenuation. these bits determine the attenuation of the adc data in mixing with the dac input. each at- tenuate step is C1.5 db ranging to C94.5 db. this registers initial state after reset is 0000 00x0. dma base count registers (ixa3:0 = 14 & 15) the dma base count registers in the AD1846 simplify integration of the AD1846 in isa systems. the isa dma controller re- quires an external count mechanism to notify the host cpu via interrupt of a full dma buffer. the programmable dma base count registers will allow such interrupts to occur. the base count registers contain the number of sample periods which will occur before an interrupt is generated on the interrupt (int) pin. to load, first write a value to the lower base count register. writing a value to the upper base register will cause both base count registers to load into the current count register. once AD1846 transfers are enabled, each sample period the current count register will decrement until zero count is reached. the next sample period after zero will generate the interrupt and reload the current count register with the values in the base count registers. the interrupt is cleared by a write to the status register. the host interrupt pin (int) will go hi during the sample period in which the current count register underflows when interrupt enable (ien) is set. the host interrupt pin (int) will go lo when the interrupt status bit (int) is cleared. [note that both the host interrupt pin and the interrupt status bit have the same name (int)]. the current count register is decremented every sample period when either the pen or cen bit is enabled and also either the transfer request disable (trd) bit or the interrupt status (int) bit are zero. note that the internal int bit will become one on counter underflow even if the external interrupt pin is not enabled, i.e., ien is zero. the current count register is decremented in both pio and dma data transfer modes. upper base count register (ixa3:0 = 14) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 14 ub7 ub6 ub5 ub4 ub3 ub2 ub1 ub0 ub7:0 upper base count. this byte is the upper byte of the base count register containing the eight most significant bits of the 16-bit base register. reads from this register return the same value which was written. the current count contained in the counters can not be read. this registers initial state after reset is 0000 0000. lower upper base count register (ixa3:0 = 15) ixa3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 15 lb7 lb6 lb5 lb4 lb3 lb2 lb1 lb0 lb7:0 lower base count. this byte is the lower byte of the base count register containing the eight least significant bits of the 16-bit base register. reads from this register return the same value which was written. the current count contained in the counters cannot be read. this registers initial state after reset is 0000 0000.
AD1846 rev. a C21C data and control transfers the AD1846 soundport stereo codec supports a dma re- quest/grant architecture for transferring data with the host com- puter bus. one or two dma channels can be supported. programmed i/o (pio) mode is also supported for control reg- ister accesses and for applications lacking dma control. pio transfers can be made on one channel while the other is per- forming dma. transfers to and from the AD1846 soundport codec are asynchronous relative to the internal data conversion clock. transfers are buffered, but the AD1846 supports no in- ternal fifos. the host is responsible for providing playback data before the next digital-to-analog conversion and removing capture data before the next analog-to-digital conversion. data ordering the number of byte-wide transfers required depends on the data format selected. the AD1846 is designed for little endian formats in which the least significant byte (i.e., occupy- ing the lowest memory address) gets transferred first. so 16-bit data transfers require first transferring the least significant bits 7:0 and then transferring the most significant bits 15:8, where bit 15 is the most significant bit in the word. in addition, left channel data is always transferred before right channel data with the AD1846. the following figures should make these requirements clear. sample 6 mono mono mono mono sample 5 sample 4 sample 3 sample 2 sample 1 time byte 1 byte 2 byte 3 byte 4 figure 7. 8-bit mono data stream sequencing sample 3 right left right left sample 3 sample 2 sample 2 sample 1 sample 1 time byte 1 byte 2 byte 3 byte 4 figure 8. 8-bit stereo data stream sequencing time mono mono sample 6 sample 5 sample 4 sample 3 sample 2 sample 1 bytes 1 & 2 bytes 3 & 4 figure 9. 16-bit mono data stream sequencing time right left sample 3 sample 3 sample 2 sample 2 sample 1 sample 1 bytes 1 & 2 bytes 3 & 4 figure 10. 16-bit stereo data stream sequencing control and programmed i/o (pio) transfers this simpler mode of transfers is used both for control register accesses and programmed i/o. the 21 control and pio data registers cannot he accessed via dma transfers. playback pio is activated when both playback enable (pen) is set and playback pio (ppio) is set. capture pio is activated when both capture enable (cen) is set and capture pio (cpio) is set. see fig- ures 11 and 12 for the detailed timing of the control register/ pio transfers. the rd and wr signals are used to define the actual read and write cycles, respectively. the host holds cs lo during these transfers. the dma capture data acknowl- edge ( cdak ) and playback data acknowledge ( pdak ) must be held inactive, i.e., hi. for read/capture cycles, the AD1846 will place data on the data7:0 lines while the host is asserting the read strobe, rd , by holding it lo. for write/playback, the host must place data on the data7:0 pins while strobing the wr signal lo. the AD1846 latches the write/playback data on the rising edge of the wr strobe. when using pio data transfers, the status register must be polled to determine when data should be transferred. note that the adc capture data will be ready (crdy hi) from the previ- ous sample period shortly before the dac playback data is ready (prdy hi) for the next sample period. the user should not wait for both adcs and dacs to become ready before initi- ating data transfers. instead, as soon as capture data is ready, it should be read; as soon as the dacs are ready, playback data should he written. values written to the xctl1:0 bits in the pin control register (ia3:0 = 10) will be reflected in the state of the xctl1:0 exter- nal output pins. this feature allows a simple method for signal- ing or software control of external logic. changes in state of the external xctl pins will occur within one sample period. be- cause their change is referenced to the internal sample clock, no useful timing diagram can be constructed. cdrq / pdrq outputs cs input cdak input data7:0 outputs rd input dben & dbdir outputs adr1:0 inputs t dbdl t rddv t adsu t cshd t cssu t dhd1 t adhd t stw t sudk2 t sudk1 figure 11. control register/pio read cycle
AD1846 rev. a C22C cdrq/ pdrq outputs cs input pdak input data7:0 inputs wr input dben output adr1:0 inputs t dbdl t adsu t cshd t dhd2 t adhd t sudk2 dbdir output t sudk1 t cssu t stw t wdsu hi figure 12. control register/pio write cycle direct memory access (dma) transfers the second type of bus cycle supported by the AD1846 are dma transfers. both dual channel and single channel dma op- erations are supported. to enable playback dma transfers, playback enable (pen) must be set and ppio cleared. to en- able capture dma transfers, capture enable (cen) must be set and cpio cleared. during dma transfers, the AD1846 asserts hi the capture data request (cdrq) or the playback data request (pdrq) followed by the hosts asserting lo the dma capture data acknowledge ( cdak ) or playback data ac- knowledge ( pdak ), respectively. the hosts asserted acknowl- edge signals cause the AD1846 to perform dma transfers. the input address lines, adr1:0, are ignored. data is transferred between the proper internal sample registers. the read strobe ( rd ) and write strobe ( wr ) delimit valid data for dma transfers. chip select ( cs ) is a dont care; its state is ignored by the AD1846. the AD1846 asserts the data request signals, cdrq and pdrq, at the rate of once per sample period. pdrq is asserted near the beginning of an internal sample period and cdrq is asserted late in the same period to maximize the available pro- cessing time. once asserted, these signals will remain active hi until the corresponding dma cycle occurs with the hosts data acknowledge signals. the data request signals will be deasserted after the falling edge of the final rd or wd strobe in the transfer of a sample, which typically consists of multiple bytes. see data ordering above for a definition of sample. dma transfers may he independently aborted by resetting the capture enable (cen) and/or playback enable (pen) bits in the interface configuration register. the current capture sample transfer will be completed if a capture dma is termi- nated. the current playback sample transfer must be completed if a playback dma is terminated. if cdrq and/or pdrq are asserted hi while the host is resetting cen and/or pen, the re- quest must be acknowledged. the host must assert cdak and/ or pdak lo and complete a final sample transfer. single-channel dma single-channel dma mode allows the AD1846 to be used in systems with only a single dma channel. it is enabled by setting the sdc bit in the interface configuration register. all cap- tures and playbacks take place on the playback channel. obvi- ously, the AD1846 cannot perform a simultaneous capture and playback in single-channel dma mode. playback will occur in single-channel dma mode exactly as it does in two-channel mode. capture, however, is diverted to the playback channel which means that the capture data request occurs on the pdrq pin and the capture data acknowledge must be received on the pdak pin. the cdrq pin will remain inactive lo. any inputs to cdak will be ignored. playback and capture are distinguished in single-channel dma mode by the state of the playback enable (pen) or capture enable (cen) control bits. if both pen and cen are set in single-channel dma mode, playback will be presumed. to avoid confusion of the origin of a request when switching be- tween playback and capture in single-channel dma mode, both cen and pen should be disabled and all pending re- quests serviced before enabling the alternative enable bit. switching between playback and capture in single-channel dma mode does not require changing the ppio and cpio bits or passing through the mode change enable state except for initial setup. for setup, assign zeros to both ppio and cpio. this configures both playback and capture for dma. then, switching between playback and capture can be effected entirely by setting and clearing the pen and cen control bits, a tech- nique which avoids having to enter the mode change enable state.
AD1846 rev. a C23C dma timing below, timing parameters are shown for 8-bit mono sample read/capture and write/playback dma transfers in figures 13 and 14. note that in single-channel dma mode, the read/ capture cycle timing shown in figure 13 applies to the pdrq and pdak signals, rather than the cdrq and cdak signals as shown. the same timing parameters apply to multibyte trans- fers. the relationship between timing signals is shown in fig- ures 15 and 16. the host interrupt pin (int) will go hi during the sample pe- riod in which the current count register underflows. this event is referenced to the internal sample period clock which is not available externally. cdrq output cdak input data7:0 outputs rd input dben & dbdir outputs t dbdl t rddv t dksu t dhd1 isa bus bclk t dkhdb t stw t drhd figure 13. 8-bit mono dma read/capture cycle pdrq output pdak input data7:0 inputs wr input dben outputs t dbdl t dksu t dhd2 isa bus bclk t dkhda dbdir output hi t stw t drhd t wdsu figure 14. 8-bit mono dma write/playback cycle cdrq/ pdrq outputs cdak/ pdak inputs data7:0 rd or wr inputs isa bus bclk left/low byte right/high byte t bwdn figure 15. 8-bit stereo or 16-bit mono dma cycle cdrq/ pdrq outputs cdak/ pdak inputs data7:0 rd or wr inputs isa bus bclk low byte high byte low byte high byte left sample right sample t bwdn figure 16. 16-bit stereo dma cycle
AD1846 rev. a C24C dma interrupt writing to the internal 16-bit base count register sets up the count value for the number of samples to he transferred. note that the number of bytes transferred for a given count will be a function of the selected global data format. the internal cur- rent count register is updated with the current contents of the upper and lower base count registers when a write occurs to the upper base count register. the current count register cannot be read by the host. read- ing the base count registers will only read back the initializa- tion values written to them. the current count register is decremented every sample pe- riod when either the pen or cen bit is enabled and also either the transfer request disable (trd) bit or the interrupt status (int) bit is zero. an interrupt event is generated after the cur- rent count register is zero and an additional playback sample is transferred. the int bit in the status register always reflects the current internal interrupt state defined above. the external int pin will only go active hi if the interrupt enable (ien) bit in the interface configuration register is set. if the ien bit is zero, the external int pin will always stay lo, even though the status registers int bit may be set. power up and reset the pwrdwn pin should be held in its active lo state when power is first applied to the AD1846. analog devices recom- mends waiting one full second after deasserting pwrdwn be- fore commencing audio activity with the AD1846. this will allow the analog outputs to fully settle to the v ref voltage level prior to system autocalibration. at any point when powered, the AD1846 can be put into a state for minimum power consump- tion by asserting pwrdwn lo. all analog and digital sections are shut down. the AD1846s parallel interface does not func- tion; all bidirectional signal lines are in high impedance state. deasserting pwrdwn by bringing it hi begins the AD1846s initialization. while initializing, the AD1846 ignores all writes and all reads will yield 1000 0000 (80h). at the conclusion of reset initialization, all registers will be set to their default values as listed in control registers above. the conclusion of the initialization period can be detected by polling the index register for some value other than 1000 0000 (80h). it is imperative to autocalibrate on power up for proper opera- tion. see next section. autocalibration the AD1846 can calibrate its adcs and dacs to minimize dc offsets. autocalibration occurs whenever the AD1846 returns from the mode change enable state and the acal bit in the interface configuration register has been set. if the acal bit is not set, the ram normally containing adc and dac offset compensations will he saved, retaining the offsets of the most re- cent autocalibration. therefore, it is imperative to autocalibrate on power up for proper operation. the completion of autocalibration can be determined by polling the autocalibrate-in-progress (aci) bit in the test and initial- ization register, which will be set during autocalibration. trans- fers enabled during autocalibration do not begin until the completion of autocalibration. the following summarizes the procedure for autocalibration: ? mute left and right aux1 and aux2 inputs, and digital mix. (it is unnecessary to mute the dac outputs, as this will hap- pen automatically.) ? set the mode change enable (mce) bit. ? set the autocalibration (acal) bit. ? clear the mode change enable (mce) bit. ? the autocalibrate-in-progress (aci) bit will transition from lo to hi within five sample periods. it will remain hi for approximately 384 sample periods. poll the aci bit until it transitions from hi to lo. ? set to desired gain/attenuation values, and unmute dac outputs (if muted), aux inputs, and digital mix. during the autocalibration sequence, data output from the adcs is meaningless. inputs to the dacs are ignored. even if the user specified the muting of all analog outputs, near the end of the autocalibration sequence, analog outputs very close to v ref will be produced at the line output. changing sample rates to change the selection of the current sample rate requires a mode change enable sequence since the bits which control that selection are in the clock and data format register. the fact that the clocks change requires a special sequence which is sum- marized as follows: ? if autocalibration will take place at the end of this sequence, then mute aux1 and aux2 inputs and the digital mix. ? set the mode change enable (mce) bit. ? in a single write cycle, change the clock frequency divide select (cfs2:0) and/or the clock source select (css). ? the AD1846 now needs to resynchronize its internal states to the new clock. writes to the AD1846 will be ignored. reads will produce 1000 0000 (80h) until the resynchronization is complete. poll the index register until something other than this value is returned. ? clear the mode change enable (mce) bit. ? if acal is set, follow the procedure described in autocalibration above. ? poll the aci bit until it transitions lo (approximately 128 sample cycles). ? set to desired gain/attenuation values, and unmute dac out- puts (if muted).
AD1846 rev. a C25C applications circuits the AD1846 stereo codec has been designed to require a mini- mum of external circuitry. the recommended circuits are shown in figures 17 through 25. analog devices estimates that the to- tal cost of all the components shown in these figures, including crystals but not including connectors, to be less than $10 in the u.s.a. in 10,000 quantities. see figure 1 for an illustration of the connection between the AD1846 soundport codec and the industry standard architec- ture (isa) computer bus, also known as the pc-at bus. note that the 74_245 transceiver receives its enable and direc- tion signals directly from the codec. analog devices recom- mends using the slowest 74_245 adequately fast to meet all AD1846 and computer bus timing and drive requirements. so doing will minimize switching transients of the 74_245. this in turn will minimize the digital feedthrough effects of the trans- ceiver when driving the AD1846, which can cause the audio noise floor to rise. industry-standard compact disc line-levels are 2 v rms cen- tered around analog ground. (for other audio equipment, line level is much more loosely defined.) the AD1846 soundport is a +5 v only powered device. line level voltage swings for the AD1846 are defined to be 1 v rms for a sine wave adc input and 0.707 v rms for a sine wave dac output. thus, 2 v rms input analog signals must be attenuated and either centered around the reference voltage intermediate between 0 v and +5 v or ac-coupled. the v ref pin will be at this intermediate voltage, nominally 2.25 v. it has limited drive but can be used as a voltage offset to an op amp input. note, however, that dc-coupled inputs are not recommended, as they provide no performance benefits with the AD1846 architecture. further- more, dc offset differences between multiple dc-coupled inputs create the potential for clicks when changing the input mux selection. a circuit for 2 v rms line-level inputs and auxiliaries is shown in figure 17. note that this is a divide-by-two resistive divider. the input resistor and 560 pf capacitor provides the single-pole of anti-alias filtering required for the adcs. if line-level inputs are already at the 1 v rms levels expected by the AD1846, the resistors in parallel with the 560 pf capacitors can be omitted. the circuit shown in figure 17 will produce gain/attenuation step sizes for the auxiliary inputs which are a function of the programmed gain/attenuation. 5.1k 5.1k 560pf l_line l_aux1 l_aux2 0.33 m f npo 5.1k 5.1k 560pf r_line r_aux1 r_aux2 0.33 m f npo figure 17. 2 v rms line-level input circuits figure 18 illustrates one example of how an electret condenser mike requiring phantom power could be connected to the AD1846. v ref is shown buffered by an op amp; a transistor like a 2n4124 will also work fine for this purpose. particular system requirements will depend upon the character- istics of the intended microphone. note that if a battery-powered microphone is used, the buffer and r 2 s are not needed. the values of r 1 , r 2 s, and c should be chosen in light of the mic characteristics and intended gain. typical values for these might be r 1 = 20 k w , r 2 = 2 k w , and c = 220 pf. 5.1k 1 m f 1/2 ssm-2135 or ad820 l_mic v ref left electret condenser microphone input 5.1k c 1 m f r_mic right electret condenser microphone input 1/2 ssm-2135 or ad820 1/2 ssm-2135 or ad820 r 1 c v ref r 1 r 2 r 2 0.33 m f 0.33 m f figure 18. phantom-powered microphone input circuit figure 19 shows ac-coupled line outputs. the resistors are used to center the output signals around analog ground. if dc-coupling is desired, v ref could be used with op amps as mentioned previously. 1 m f 47k l_out 1 m f 47k r_out figure 19. line output connections a circuit for headphone drive is illustrated in figure 20. drive is supplied by +5 v operational amplifiers. the circuit shown ac couples the line output to the headphones. headphone left headphone right l_out r_out 470 m f 20k ssm-2135 v ref 18k 18k 470 m f 20k figure 20. headphone drive connections
AD1846 rev. a C26C figure 21 illustrates reference bypassing. v ref _f should only be connected to its bypass capacitors. 10 m f 10 m f v ref 0.1 m f v ref f _ figure 21. voltage reference bypassing figure 22 illustrates signal-path filtering capacitors, l_filt and r_filt. the 1.0 m f capacitors required by the AD1846 can be of any type. note that AD1846s will perform satisfacto- rily with 0.1 m f capacitors; however, low frequency performance will be degraded. r_filt 1.0 m f l_filt 1.0 m f figure 22. external filter capacitor connections the crystals shown in the crystal connection circuitry of figure 23 should be fundamental-mode and parallel-tuned. note that using the exact data sheet frequencies is not required and that external clock sources can be used to drive the crystal inputs. (see the description of the cfs2:0 control bits above.) if using an external clock source, apply it to the crystal input pins while leaving the crystal output pins unconnected. attention should be paid to providing low jitter external input clocks. xtal1o xtal1i 20?4pf 24.576mhz 20?4pf xtal2o xtal2i 20?4pf 16.9344mhz 20?4pf figure 23. crystal connections low cost ceramic resonators may be substituted for the crystals to supply the time base to the AD1846. analog devices recommends a pull-down resistor for pwrdwn . good, standard engineering practices should be applied for power supply decoupling. decoupling capacitors should be place as close as possible to package pins. if a separate analog power supply is not available, we recommend the circuit shown in figure 24 for using a single +5 v supply. this circuitry should be as close to the supply pins as is practical. +5v supply 1.6 w 1 m f 0.1 m f v dd 0.1 m f ferrite/inductor v cc v dd 0.1 m f v dd 0.1 m f v dd 0.1 m f v dd 0.1 m f v dd 0.1 m f v dd 0.1 m f 0.1 m f 0.1 m f 1 m f v cc 1 m f ferrite/inductor figure 24. recommended power supply bypassing analog devices recommends a split ground plane as shown in figure 25. the analog plane and the digital plane are connected directly under the AD1846. splitting the ground plane directly under the soundport codec is optimal because analog pins will be located above the analog ground plane and digital pins will be located directly above the digital ground plane for the best isolation. the digital ground and analog grounds should be tied together in the vicinity of the AD1846. other schemes may also yield satisfactory results. if the split ground plane recommended here is not possible, the AD1846 should be entirely over the analog ground plane with the 74_245 transceiver over the digital plane. digital ground plane analog ground plane gndd r_aux2 AD1846 gndd r_filt figure 25. recommended ground plane
AD1846 rev. a C27C outline dimensions dimensions shown in inches and (mm). p-68a 68-lead plastic leaded chip carrier 0.029 (0.74) 0.027 (0.69) 0.019 (0.48) 0.017 (0.43) 0.175 (4.45) 0.169 (4.29) 0.925 (23.50) 0.895 (22.73) 0.104 (2.64) typ 0.050 (1.27) typ 0.954 (24.23) 0.950 (24.13) sq 0.995 (25.27) 0.885 (22.48) sq 44 43 26 10 9 60 61 27 top view pin 1 identifier index page product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 electrical specifications . . . . . . . . . . . . . . . . . . . 2 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 audio functional description . . . . . . . . . . . . . . 9 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 analog mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 analog-to-digital datapath . . . . . . . . . . . . . . . . . . . . . . . . 9 digital-to-analog datapath . . . . . . . . . . . . . . . . . . . . . . . . 9 digital mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 analog outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 digital data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 power supplies and voltage reference . . . . . . . . . . . . . . . 10 clocks and sample rates . . . . . . . . . . . . . . . . . . . . . . . . . 10 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . 11 control register architecture . . . . . . . . . . . . . . . . . . . . . . 11 direct control register definitions . . . . . . . . . . . . . . . . . 12 indirect control register definitions . . . . . . . . . . . . . . . . 14 data and control transfers . . . . . . . . . . . . . . . 21 data ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 control and programmed i/o (pio) transfers . . . . . . . . 21 direct memory access (dma) transfers . . . . . . . . . . . . . 22 single-channel dma . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 dma interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 power up and reset . . . . . . . . . . . . . . . . . . . . . . . . . 24 autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 changing sample rates . . . . . . . . . . . . . . . . . . . . . 24 applications circuits . . . . . . . . . . . . . . . . . . . . . . . 25 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AD1846 rev. a C28C c1966C5C10/94 printed in u.s.a.

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